ET-3400 ROM - testing /CE and /OE options

The original ROM does not have a separate /OE and /CE pins, instead it puts data onto the database once the four CS pins meet the required conditions. This is not uncommon for ROMs of this vintage. We are using a modern replacement EEPROM and it has separate /CE (Chip Enable) and /OE (Output Enable) pins.

I have seen various ways to use those pins in other memory expansion projects. Sometimes one pin is tied to GND and the other pin is used to enable the chip to output the data onto the bus. At other times both pins are tied together so that the both go low or high at the same time.

This gives several options:

Option 1. /CE tied low permanently and /OE set low to read data, then high to disable output.

Option 2. /OE tied low permanently and /CE set low to read data, then high to disable output.

Option 3. /CE and /OE tied together and both set low to read, or high to disable output.

The data sheet shows the following Operating Modes:


Going by this you would set /CE low and /OE low for read, and to disable the output (High Z) the /CE doesn't matter (X) and /OE is high (VIH).

Further down the data sheet it shows the Read mode waveforms:


If you go by the waveforms you would set /CE low, then /OE low just before the data is placed onto the data bus. I don't want to have separate timing for the signals or that would involve extra circuitry to delay one of the signals, but it looks like you could tie them together as an option, and it's implied in the Operating Modes too.

So I tested all 3 methods and the results were a little surprising to me.

Option 1 was the only mode that worked properly. Option 2 and 3 almost worked as they could boot to the 'CPU UP.' prompt. However after that they failed to respond to keypad entry.

Option 2 and 3 could be failing due to the speed of the EEPROM, or it could be delays due to running the circuit on a breadboard, but I've decided to use Option 1 as it seems to agree with the data sheets and it worked. I didn't pull out my CRO to do any measurements to find out if I could have done better or whether a different speed EEPROM or TTL chip would have worked better.

You might have noticed I didn't use any decoupling caps in my circuit diagram, but I did use them in my prototype. The reason for my choice is that there is already a decoupling cap for the original ROM, and this board will be very small so the traces are short. All the parts on the PCB will be soldered and part of the reason for having the decoupling caps is to cater for power drop over each physical connection due to switching surges as you would see in a socketed design. On the prototype I used decoupling caps because of the jumper wires and ribbon cable used and numerous sequential unsoldered connections.

And next I'll be working on the PCB layout...

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